DDR3 memory initialization basics on Intel Sandybrige platforms
level: advanced
Coreboot on SandyBridge has an open source memory initilization, that give inside of todays memory controllers. I'll give a short introduction into memory initilization in general and the evolution of DDR memory. What looks complex at first, due to decisions made to cheapen DRAM, boils down to a simple workflow. A short excursion will describe how to use coreboot to bypass memory scrambling and DRAM reset to dump data that is still in memory and not accessible while in normal operation mode. After describing the current state, I'll give an overwiew of future plans and possible features to be implemented.